Digital circuits logic design lab manual

This means that sometimes just single cells will remain at the end. In this example, all the cells containing a 1 were covered with two boxes. This means that if the conditions for either box are true, the output will be true.

This also means that the simplified Boolean equation will only have two terms. The term for each box can be determined by observing which variables are constant throughout each cell of that box. For the red box, only W remains constant through the four cells. D switches from the top row to the bottom row, and P switches from the left column to the right column. For the blue box, P and remains constant through the two cells, while W switches from the left cell to the right cell.

The two boxes yield the simplified Boolean equation shown in Figure This equation meets the conditions in the truth table in Table 1 and achieves the desired result with the minimum number of logic elements. Boolean logic is applied to digital circuitry through the use of simple logic gates. There are symbols for each of these gates, and the connections between them are represented by lines running from the output of one gate to the input of another.

A line can connect only one output to each input. Only the first three will be used in this lab Figure The NOT gate is the simplest of the three. It is an inverter. It has one input and produces its opposite as the output. For example, if a 1 is the input to a NOT gate, a 0 value is outputted, as seen in Table 2. The symbol for the operation is a horizontal bar over the variable.

The truth table for a NOT gate is shown in Table 2. The AND gate performs a multiplication operation on its inputs. If all the inputs are true, the output is also true. But if either of the inputs is false, the output is also false. The truth table for an AND gate is shown in Table 3.

An OR gate performs an addition operation on its inputs. If either of the inputs is true, the output is also true. But if all the inputs are false, the output is also false.

An OR gate can have two or more inputs, but for this lab, it will have two inputs denoted by A and B in Table 4. The truth table for an OR gate is shown in Table 4. Lastly, a combinational logic circuit can be created using the simplified equation.

Then, the P and inverted D are inputted into an AND gate, as denoted by them being multiplied in figure Finally, the result of the AND operation between the P and inverted D and the W is inputted into an OR gate, as denoted by the addition function in figure The final combinational logic circuit can be seen in Figure Integrated circuits IC can be used to prototype a combinational logic circuit on a breadboard. These devices are small assemblies of electronic components that have been combined into a single unit.

In this lab, the IC chips consist of logic gates that can be wired to prototype the logic circuit Figure 3. The number of rows is determined by the number of possible combinations. To illustrate a truth table and additional concepts that will be introduced, an example problem statement will be given. Think of an ATM that has three options: print a statement, withdraw money, or deposit money. The ATM will charge a fee to 1 withdraw money or 2 print a statement without depositing money.

The intent of the problem is to develop a Boolean equation and logic circuit that will determine after which possible combination of actions will someone get charged a fee.

First, a truth table should be made for all the possible combinations of inputs. The inputs are the ATM's three functions.

Let variable stand for printing a statement, for withdrawing money, and for depositing money. There is one output, which is whether or not the ATM will charge a fee. The output will be denoted by. The truth table in Table 1 shows all the possible combinations of the inputs and their corresponding outputs.

Boolean logic is applied to digital circuitry through the use of simple logic gates. There are symbols for each of these gates, and the connections between them are represented by lines running from the output of one gate to the input of another.

A line can connect only one output to each input. Only the first three will be used in this lab Figure 1. The NOT gate is the simplest of these three. It is an inverter. It has one input and produces its opposite as the output. For example, if a 1 value is put into a NOT gate, a 0 value is outputted, as seen in Table 2. The symbol for the operation is a horizontal bar over the variable. The truth table for a NOT gate is shown in Table 2.

The AND gate performs a multiplication operation on its inputs. If all the inputs are true, the output is also true. But if either of the inputs is false, the output is also false. The truth table for an AND gate is shown in Table 3. An OR gate performs an addition operation on its inputs. If either of the inputs is true, the output is also true.

But if all the inputs are false, the output is also false. An OR gate can have two or more inputs, but for this lab, it will have two inputs denoted by A and B in Table 4. The truth table for an OR gate is shown in Table 4. A truth table is used to write a Boolean equation for a problem. All the combinations that yield an output of 1 are kept, and the equation is written. This is called a Sum of Products solution.

Only the combinations that yield an output of 1 are kept because the Boolean equation intends to represent a quantitative function for when the result will have a value of true when a fee is charged in the example of the ATM machine. The combinations that yield an output of 0 are essentially discarded because there is no interest in when the result has a false value. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two binary conditions low 0 or high 1 , represented by different voltage levels.

The logic state of a terminal can, and generally does, change often, as the circuit processes data. Procedure: Connect the circuit according to the pin configuration of the ICs as mentioned in the datasheets and check the truth tables. Now Implement the circuit from the minterms again and verify the results with the initial given expression. Figure 2. AND Gate Figure 3. Are they both the same or not? And why? NOT 2. AND 3. OR After doing this, implement the given expression on the trainer board.

Background: A parity bit, or check bit, is a bit added to the end of a string of binary code that indicates whether the number of bits in the string with the value one is even or odd.

Parity bits are used as the simplest form of error detecting code. There are two variants of parity bits: even parity bit and odd parity bit. In case of even parity, the parity bit is set to 1 if the count of ones in a given set of bits not including the parity bit is odd, making the count of ones in the entire set of bits including the parity bit even.

If the count of ones in a given set of bits is already even, it is set to a 0. When using odd parity, the parity bit is set to 1 if the count of ones in a given set of bits not including the parity bit is even, making the count of ones in the entire set of bits including the parity bit odd. When the count of set bits is odd, then the odd parity bit is set to 0. Background theory: A half adder is a combinational circuit that adds two binary inputs.

It gives two outputs, S as the sum and C as the carry of the inputs. A full adder is a combinational circuit that adds three binary inputs X, Y and Z. The input Z is the carry input from another addition. Implement it on trainer and verify the results. Implement it on the trainer and verify the results: Figure 5. FA is full adder.

The operation depends upon Cin. Objective: To familiarize student with basic working of multiplexer and implementation of 4x1 mux. Background Theory: A MUX is a combinational circuit that can be used to select data and produce it at the output. It has a lot of applications. There are many scenarios in which we have to select a particular data and produce it at the output. There are many scenarios in which we must use such devices. It is derived from the single-loop storage element.

The latch has two inputs labeled as S for set and R for reset. The operation of a basic NOR and NAND latches can be modified by providing an addition control bit that determines when the state of the latch can be changed. Implement the circuits and verify the results. This is done in the D Latch. Figure 9. Exercise in Lab: Fill in the truth table for D Flipflop. Background Theory: The basic concept in the implementation if the state machine is that we should know about the truth table, excitation table of the JK flipflop and transition table.

This lab contains almost all the concepts that have been taught during the DLD course. Fill in the following Blanks. It provides the designer entry into the world of large, complex digital systems design. The Verilog language provides the digital system designer with a means of describing a digital system at a wide range of levels of abstraction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels.

It also fulfils the need for verifying the design for functionality and timing constraints like propagation delay setup and hold times.