Digital fundamentals 10th edition answers

An open pin 11 would cause this problem. Changes required for the system to incorporate a 15 s left turn signal on main: 1.

Change the 2-bit gray code sequence to a 3-bit sequence. Add decoding logic to the State Decoder to decode the turn signal state. Change the Output Logic to incorporate the turn signal output.

Change the Trigger Logic to incorporate a trigger output for the turn signal timer. Add a 15 second timer. It will be corrected to match Figure in the 2nd printing.

Counter implementation is straightforward from input expressions. The states with an asterisk are the transition states that produce glitches on the decoder outputs. The glitches are indicated on the waveforms in Figure Problem by short vertical lines.

See the timing diagram in Figure which is expanded to show the delays. Any glitches can be prevented by using CLK as an input to both decode gates. For the digital clock in Figure of the text reset to , the binary state of each counter after sixty-two Hz pulses are: Hours, tens: Hours, units: Minutes, tens: Minutes, units: Seconds, tens: Seconds, units: Q0 also grounded.

First, determine the correct waveforms and observe that Q0 is correct but Q1 and Q2 are incorrect in Figure in the text. Obviously, the counter is going through all of its states.

This means that the 63C on its parallel inputs is not being loaded. Possible faults are:. Th DIV 6 is the tens of minutes counter. The apparent counter sequence is shown in the table. Actual State of Ctr. The decode 6 gate interprets count 4 as a 6 and clears the counter back to 0 actually Thus, the apparent not actual sequence is as shown in the table.

There are several possible causes of the malfunction. First check power to all units. Other possible faults are listed below. Sensor Latch Action: Disconnect entrance sensor and pulse sensor input. Observation: Latch should SET.

Conclusion: If latch does not SET, replace it. NOR gate Action: Pulse sensor input. Observation: Pulse on gate output. Conclusion: If there is no pulse, replace gate. Action: Pulse sensor input. Observation: Counter should advance. Conclusion: If counter does not advance, replace it. Output Interface Action: Pulse sensor input until terminal count is reached. Observation: If all previous checks are OK, sensor or cable is faulty. Conclusion: Replace sensor or cable. The expressions for the D0 and the D1 flip-flop inputs in the sequential logic portion of the system were developed in the System Application Activity.

Figure shows the NAND implementation. The approach is to preset the hours and minutes counters independently, each with a fast or slow preset mode. The seconds counter is not preset. One possible implementation is shown in Figure Chapter 9 7.

Chapter 9 Section Bidirectional Shift Registers Since the LSB flip-flop works during serial shift, the problem is most likely in gate G3. An open D3 input at G3 will cause the observed waveform. The NAND negative-OR gate input connected to the first column is shorted to ground or open, preventing a switch closure transition.

Depress switches one at a time and observe the key code output according to the following Table 1. Contents of Data Output Register remain constant. Contents of both registers do not change. The purpose of the Security Code logic is to accept a 4-digit code, compare it with a stored code, and if the codes match, to disarm the system for entry.

The states of shift registers A and B after each key closure when entering are: After key 7 is pressed: Shift register A contains Shift register B contains After key 6 is pressed: Shift register A contains Shift register B contains After key 4 is pressed: Shift register A contains Shift register B contains After key 5 an incorrect entry is pressed: Shift register A contains Shift register B contains Figure shows only the 74LS, 74LS, and 74LS portions of the circuit that require modification for bit conversion.

Register A requires 8 bits and can be implemented with one Register B requires 16 bits and can be implemented with two s.

They are random access memories because any address can be accessed at any time. You do not have to go through all the preceding addresses to get to a specific address. Address bus provides for transfer of address code to memory for accessing any memory location in any order for a read or a write operation. Address AA0 Contents QQ0 The first byte goes into FFF A hard disk is formatted into tracks and sectors.

Each track is divided into a number of sectors with each sector of a track having a physical address. Hard disks typically have from a few hundred to a few thousand tracks. Seek time is the average time required to position the drive head over the track containing the desired data. The latency period is the average time required for the data to move under the drive head. Magnetic tape has a longer access time than disk because data must be accessed sequentially rather than randomly.

A WORM write-once-read-many is an optical medium in which data can be written once and read many times. The correct checksum is The actual checksum is The second bit from the left is in error. A single checksum will not isolate the faulty chip. It will only indicate that there is an error in one of the chips. On first digit entry, the register state is On second digit entry the register state is The purpose of the switch memory is to store a 4-digit security code and permit easy code change.

Typically, an exclusive-OR gate is used to determine the polarity of the output. When a 1 is applied to one input of the XOR gate, the output of the XOR is the complement of the signal on the other input. When a 0 is applied to one input of the XOR, the signal on the output of the XOR is the same as the signal on the other input.

Since the D0 upper input of MUX 5 is selected, the macrocell is configured for combinational logic. Since the D1 lower input of MUX 5 is selected, the macrocell is configured for registered logic. The macrocell is configured for registered logic because the D1 input of MUX 8 is selected, allowing the flip-flop output to pass through. Each CLB is made up of a number of logic modules with a local interconnect.

Each logic module typically consists of a look-up table LUT and associated logic. From the output of Capture register A, the data go through the upper MUX and are clock into Capture register B on the trailing edge of the clock pulse. The data from the internal programmable logic pass through the selected MUX and through the output buffer to the pin. The data are applied to the input pin and go through the selected MUX to the internal programmable logic. From the output of Capture register A, the data go through the upper MUX and are clocked into Capture register B on the trailing edge of the clock pulse.

The data also appear on the SDO. The bold-faced code will appear on the logic inputs in the sequence shown. Only four are needed to produce the complements of A, B, C, and D. Two can be eliminated. One can be eliminated. Output of 3-bit converter: , , , , , , , , , , , , , , , , , , , Comment Greater than Vin. Reset MSB. Less than Vin. Keep the 1. Equal to Vin. Keep the 1 final state. The purpose of analog-to-digital conversion is to change an analog signal into a sequence of digital codes that represent the amplitude of the analog signal with respect to time.

The purpose of digital-to-analog conversion is to change a sequence of digital codes into an analog signal represented by the digital codes.

Program address generate PG. The program address is generated by the CPU. Program address send PS. The program address is sent to the memory. Program access ready wait PW. A memory read operation occurs. Program fetch packet receive PR. The CPU receives the packet of instructions.

Instruction dispatch DP : Instruction packets are split into execute packets and assigned to functional units; Instruction decode DC : Instructions are decoded. A bus is a set of physical connections over which data and other information is transferred in a computer according to a standard set of specifications.

A port is a physical interface on a computer through which data is passed to and from peripherals. The basic elements of a microprocessor are arithmetic logic unit ALU , instruction decoder, control unit, and register array. A microprocessor performs arithmetic operations, logic operations, data movements, and decision functions. Groups of Pentium instructions are: data transfer, arithmetic and logic, bit manipulation, loops and jumps, strings, subroutines and interrupts, and control.

Pipelining is the process by which a microprocessor begins executing the next instruction before the previous instruction has been completed. Multitasking is the process of executing more than one program at a time.

Multithreading is the process of executing different parts threads of a single program simultaneously. Pipelining is the process of fetching and executing at the same time so that more than one instruction can be processed simultaneously.

The code segment CS register contains 0F05 and the instruction pointer contains A flag is a bit stored in the flag register that is set or cleared by the processor. A flag indicates a status or a control condition. A status flag is an indicator of a condition after an arithmetic or logic operation. A control flag alters processor operations under certain conditions.

The flowchart in Figure shows the process for adding numbers from one to ten and saving the results in a memory location named TOTAL. The flowchart in Figure shows how you can count the number of bytes in a string and place the count in a memory location called COUNT. When the instruction mov ax, [bx] is executed, the word in memory pointed to by the bx register is copied to the ax register. A compiler is a program that compiles or translates a program written in high-level language and converts it to machine code.

The local bus is the collection of buses interfacing directly with the processor. The PCI bus is used for expansion devices and is connected to the local bus through a bus controller.

Plug-and-Play refers to self-configuring hardware that can be installed into and used in a computer system without the need for manual installation of jumpers or setting of switches. ISA is an 8- or bit 8. PCI supports 3. DCE stands for data communications equipment, such as a modem.

DTE stands for data terminal equipment, such as a computer. Since there are eight instruments already on the bus and the limit is fourteen, six more instruments can be connected. A controller is sending data to two listeners. The first two bytes of data 3F and 41 go to the listener with address A. The second two bytes go to the listener with address B. The network in a can operate at the highest frequency because the driving gate has fewer loads.

ON: high voltage on base forward-biases the base-emitter junction. OFF: insufficient voltage on base to forward-bias the base-emitter junction. OFF: emitter is more positive than the base which reverse-biases the base-emitter junction. OFF: base and emitter at same voltage. No forward bias. Connect the unused input of the NOR gate to ground.

Connect a pull-up resistor to the open collector of the NOR gate value depends on load. The driving gate output is LOW, it is sinking current from 2 unit loads. G1 output is HIGH, it is sourcing 6 unit loads. Worst case for determining minimum Rp is when only one gate is sinking all of the current 40 mA maximum. For 10 UL: For each gate:. Segment d is used in letters b, C, d, and E. The hexadecimal code for each letter is as follows: b—; C—; d—; E— Segment e is used in letters A, b, C, d, and E.

The hexadecimal code for each letter is as follows: A—; b—; C—; d—; E— The expression for segment e is. The hexadecimal code for each letter is as follows: A—; b—; C—; E— The expression for segment f is.

Segment g is used in letters A, b, d, and E. The hexadecimal code for each letter is as follows: A—; b—; d—; E— The expression for segment g is. An inverter in each segment output will provide an active-HIGH.

The additional input to the outlet valve control is T for temperature. The corn syrup must be at a specified temperature for proper viscosity before the syrup can be released into the mixing vat. Once the tank starts draining, the outlet value remains open on until the minimum level is reached. The temperature control circuit could be modified by eliminating the LSD in the BCD code for the measured temperature.

The system remains in the first state 00 for 25 s if there is a vehicle on the side street or as long as there is no vehicle on the side street. The expression for the condition producing a transition from the first state to the second state is TLVs.

If system is in first state , it goes immediately to second state for 4 s and then to fifth state for 15 s and then back to first state If system is in third state , it goes immediately to fourth state for 4 s and then to fifth state for 15 s and then back to first state If system is in either second or fourth states, the short timer is retriggerd and the system remains in that state for another 4 s before going to the fifth state.

The resistor and capacitor values for the 25 s timer are determined as follows. The resistor and capacitor values for the 4 s timer are determined as follows. The resistor and capacitor values for the 10 kHz oscillator are determined as follows. Real time is determined by connecting a Multisim probe to the one-shot output and measuring its ontime. Simulation time is determined by connecting a virtual oscilloscope to the one-shot output and measuring the pulse-width.

The combinational logic portion of the system was modified in Chapter 6 to accommodate a pedestrian input to turn both lights red for 15 s. To accomplish this exercise, the student must recognize that the timing circuits and the sequential logic must also be modified.

Timing circuit modification: An additional timer configured as a one-shot with a 15 s output pulse is addded:. Sequential logic modification: A third flip-flop is added. First, the next-state table is modified to accommodate the pedestrian input P.

Karnaugh map simplification would not be feasible. If you wish to minimize the expressions, the Quine-McCluskey method can be used but will be left as an exercise that can be assigned to students. The purpose of the OR gate is to produce a trigger when a key is pressed in order to generate the clock pulses for the system. The security code logic can be modified for a 5-digit code by moving the HIGH parallel input of shift register C back one position. It would then take five clock pulses to shift the 1 to the output.

The memory and code selection logic can be modified for a 5-bit code by adding a DIP switch with resistor pull-ups, four more AND gates, changing the OR gates to five inputs, and changing the shift register from four bits to five bits. The waveform for SEGe is shown in the following figure. The waveform for SEGf is shown in the following figure. The waveform for SEGg is shown in the following figure. Laboratory Instrument Familiarization Instructor Multisim Solutions There are Multisim files for Multisim 9 and Multisim 10 files for seven experiments 5, 8, 10, 12, 18, 19, and 23 on the companion website.

Within 48 hours after registering, you will receive a confirming e-mail, including an instructor access code. Once you have received your code, go to the site and log on for full instructions on downloading the materials you wish to use.

The Multisim suffix is. Review Quiz Answers-Chapter 4 1. Define GDP and distinguish between a final good and an intermediate good.

Provide examp. Answers will vary, but should include the notion that each activity provides benefits. Pearson Prentice Hall.

All rights reserved. Printed in the United States of America. This publication is protected by Copyright and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise.

For information regarding permission s , write to: Rights and Permissions Department. Go to www. Within 48 hours after registering you will receive a confirming e-mail including an instructor access code. Once you have received your code, go the site and log on for full instructions on downloading the materials you wish to use. Digital data can be transmitted and stored more efficiently and reliably than analog data.

Also, digital circuits are simpler to implement and there is a greater immunity to noisy environments. Section Arithmetic Operations with Signed Numbers Section Hexadecimal Numbers Section Octal Numbers Section Digital Codes The Gray code makes only one bit change at a time when going from one number in the sequence to the next number.

Section Error Detection Codes Code b has five 1s, so it is in error. Codes a and c are in error because they have an even number of 1s. Open navigation menu.

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